In fabricating a semiconductor device, it is often desired to accurately align upper and lower layers. To this end, overlay accuracy can be achieved by forming monitoring patterns (or keys). The monitoring patterns may be formed in, for example, a scribe lane region of a wafer, between semiconductor devices (which may be later separated or singulated from each other), e.g., to avoid affecting the operation of circuits of a semiconductor device formed in the circuit region. A scribe region may be an area between semiconductor devices integrally formed in a wafer such that separation of the semiconductor devices from each other along the scribe region (e.g., by cutting the wafer at the scribe region) would not affect normal operations of the semiconductor devices. However, the monitoring patterns may be damaged by, for example, a chemical mechanical polishing (CMP) process in fabricating the semiconductor device. In order to achieve accurate alignment of upper and lower layers, the monitoring patterns should remain at least to a substantial amount even after being damaged during a particular process.
Korean Patent No. 0887064 discloses an overlay venires and a forming method thereof.